A typical prior art voltage clamp, as shown in FIG. 1, utilizes a single PMOS transistor T1 to limit the voltage at output node N. In this circuit the output load, represented by resistor R.sub.L, is driven by a current source I. When the output voltage at node N exceeds the input voltage by V.sub.th (the threshold voltage of T1), T1 turns on and begins to conduct current from node N to ground, effectively limiting the output voltage at node N to V.sub.th above the input voltage. Equivalent bipolar clamp circuits are also known in the prior art.
A significant disadvantage of the single-transistor clamp circuit arises from its limited transconductance, which in turn means that it does not turn on very hard; i.e., above V.sub.th the slope of its I-V characteristic is not as nearly vertical as desired. MOSFET transconductance is proportional to the gate width-to-length ratio (W/L). Since gate length is typically set by the design rules of a given IC process, increasing transconductance by a factor M generally implies increasing W by a similar factor. Unfortunately, this approach significantly increases the area of the MOSFET, area which is frequently at a premium in state-of-the-art, densely packed ICs. Once again, similar considerations apply to bipolar clamp circuits.
Thus, a need remains in the art for a voltage clamp IC which provides increased transconductance without significantly increased circuit area as compared to single-transistor clamp circuits.